1. Field of the Invention
The present invention relates generally to dynamic logic in computers and, more particularly, to a system and method for clocking logic blocks having cascaded self-timed dynamic logic gates, for example, "mousetrap" logic gates.
2. Related Art
Recently, a functionally complete family of self-timed dynamic logic gates was developed by Jeffry Yetter of Hewlett-Packard Company, Fort Collins, Colo., U.S.A. These self-timed dynamic logic gates were configured to implement a vector logic system. In the proposed vector logic system, more than two valid logic states are propagated through the logic. Furthermore, by using a precharge on the mousetrap logic gates, a monotonic progression of logic evaluations is implemented.
In a monotonic progression, only one direction of logic transition is considered. For example, in mousetrap logic gates, only the logic transition from a logic low to a logic high is considered, not the logic transition from a logic high to a logic low. As a result of the implementation of a monotonic progression, problems associated with static hazards are eliminated.
Furthermore, because a vector logic state in the present invention is encoded in a physical way which allows for an invalid state and because dynamic precharging is implemented, outputs from a mousetrap logic block, comprising one or more cascaded mousetrap logic gates, may be "self-timed," or configured to operate asynchronously with respect to the clock source providing the precharge signals. In other words, clocks or other charging signals are used to merely precharge the mousetrap logic gates; the clocks do not dictate progression of the logic evaluation through the cascaded mousetrap logic gates. Triggering of each individual mousetrap logic gate is accomplished by a successful logic evaluation performed by the corresponding logic associated with the mousetrap logic gate. Hence, when using the vector logic system with mousetrap logic gates, two significant features can be determined from each vector output: (1) when the vector output is valid, thereby eliminating the need for a conventional valid clock signal, and (2) the value of the vector output when it is valid.
When mousetrap logic gates are cascaded in series, a vector input will proceed through the gates in a self-timed manner. Each successive gate will perform a logic evaluation on its corresponding vector inputs when the gate determines them to be valid. Moreover, the cascaded mousetrap logic gates can be precharged in parallel by a clock and then permitted to perform logic evaluations on the vectors. However, the clocking system must be configured to permit enough time for the logic evaluations to proceed entirely through the cascaded network. Further, the clocking system must be configured to permit enough time for all cascaded gates to precharge. As a result of the foregoing requirements, the vector output of the cascaded gates must oftentimes wait for a clock edge before it can proceed to another mousetrap logic block. Thus, much time is wasted.
Consequently, a need exists for a self-timed clocking system and method for optimally exploiting the self-timed nature of mousetrap logic gates and any other dynamic logic gates which have self-timed attributes.